Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
US7195984B2 · kind B2 · utility
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Key dates
| Filing date | Nov 22, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
Abstract
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.