High-voltage MOS transistor
US7196375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0221
Abstract
A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.