Method and structure to develop a test program for semiconductor integrated circuits
US7197417B2 · kind B2 · utility
27Cited by
8References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.