Method and apparatus for detecting faults using principal component analysis parameter groupings
US7198964B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Jan 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for identifying faults in a semiconductor fabrication process includes storing measurements for a plurality of parameters of a wafer in the semiconductor fabrication process. A first subset of the parameters is selected. The subset is associated with a feature formed on the wafer. A principal component analysis model is applied to the first subset to generate a performance metric. A fault condition with the wafer is identified based on the performance metric. A system includes a data store and a fault monitor. The data store is adapted to store measurements for a plurality of parameters of a wafer in a semiconductor fabrication process. The fault monitor is adapted to select a first subset of the parameters, the subset being associated with a feature formed on the wafer, apply a principal component analysis model to the first subset to generate a performance metric, and identify a fault condition with the wafer based on the performance metric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.