Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

US7198993B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Howard L. Tigelaar · Friendswood, US
• Gabriel G. Barna · Richardson, US
• Olivier Faynot · Seyssinet-Pariset, FR

Key dates

• Filing date: Dec 13, 2004
• Grant date: Apr 3, 2007
• Expiry date: Sep 30, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01

Abstract

A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).