Planarization method of manufacturing a superjunction device
US7199006B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method includes providing trenches and mesas in the substrate, implanting, at an angle, a dopant of the first conductivity into a sidewall of a mesa and implanting, at an angle, a dopant of a second conductivity into the mesa at another sidewall. The method includes oxidizing the sidewalls and bottoms of each trench and tops of the mesas to create a top oxide layer, etching back the top oxide layer to expose a portion of the mesa, depositing an oxide layer to cover the etched back top layer and mesa and planarizing the top surface of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.