Semiconductor package suitable for high voltage applications
US7199461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Mar 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.