Over-voltage tolerant bus hold circuit and method therefor
US7199614B2 · kind B2 · utility
1Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Jun 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment a bus hold circuit decouples an inverter of the bus hold circuit from an operating voltage responsively to an input receiving a signal having a voltage that is approximately equal to or greater than the value of the operating voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.