Memory including a transfer gate and a storage element
US7200036B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2005 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each memory cell is composed of a storage layer (2) for storing therein information based on the magnetization state of a magnetic material, a magnetization fixed layer (4) provided on the storage layer (2) through an intermediate layer (3), a storage element (10) for applying an electric current in the laminating layer direction to change the direction of magnetization of the storage layer (2) thereby to record information on the storage layer (2) and a memory cell including a selection transistor, wherein a polarity which requires a large amount of electric current to record information and a polarity by which a large amount of saturation electric current can be supplied to the selection transistor are made coincident with each other. A size of each memory cell including the selection transistor can be decreased to the minimum by suppressing influences of asymmetric property of a write electric current and a memory can integrate the memory cells at a high density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.