Method and circuit arrangement for reading from a flash/EEPROM memory cell
US7200042B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2005 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Sep 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor. According to the invention, it is provided that firstly, in a first step, the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. In a second step, it is provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage. In a third step, provision is made for generating, with the aid of the predetermined reference current, a reference voltage that is dependent on the channel resistance of the reference memory transistor. In a fourth step, the reference voltage generated is applied to the gate of the memory transistor and the gate of the reference memory trans…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.