Semiconductor memory and burn-in test method of semiconductor memory
US7200059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Oct 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.