On chip network that maximizes interconnect utilization between processing elements
US7200137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Apr 3, 2007 |
| Priority date | — |
| Expiry date | Jun 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.