Integrated circuit with copper interconnect and top level bonding/interconnect layer
US7202546B2 · kind B2 · utility
0Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.