NPN Darlington ESD protection circuit
US7203050B2 · kind B2 · utility
3Cited by
15References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Apr 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.