HDL co-simulation in a high-level modeling system
US7203632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.