Non-fenced list DMA command mechanism
US7203811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2003 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.