Asynchronous control of memory self test
US7203873B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.