Method of fabricating a flash memory cell
US7205194B2 · kind B2 · utility
4Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.