Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup
US7205209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Feb 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a stacked dielectric layer for suppressing electrostatic charge buildup. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer by performing a plasma treatment on the dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.