Polymer memory device with electron traps
US7205595B2 · kind B2 · utility
0Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Apr 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.