Phase error correction circuit for a high speed frequency synthesizer
US7205798B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jan 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for reducing the phase error in an NCO clock output to reduce the clock jitter. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to obtain a substantially glitch-free, high-speed operation. During the first step, the output of the NCO is phase shifted to the closest quarter portion of a cycle of a clock signal. A second correction step is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.