Clocked standby mode with maximum clock frequency
US7205829B2 · kind B2 · utility
5Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a period of the first clock signal is less than a period of the second clock signal and the voltage generator is selectively enabled in conjunction with the second clock signal when the period of the second clock signal is less than the period of the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.