Memory system with parallel data transfer between host, buffer and flash memory
US7206233B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Oct 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.