Array redundancy supporting multiple independent repairs
US7206236B1 · kind B1 · utility
1Cited by
1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 12, 2006 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.