Methods and apparatus for implementing standby mode in a random access memory
US7206245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jun 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the generator system a state control signal that commands the generators to be in an active state or a standby state, and a self-refresh oscillator that generates a self-refresh clock signal having a period suitable to refresh memory cells of the memory device. The controller uses the self-refresh clock signal to delay transitions of the state control signal from the active state to the standby state relative to corresponding state changes of at least one external signal received by the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.