Method and apparatus for a network processor having an architecture that supports burst writes and/or reads
US7206857B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2002 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.