Pitch multiplication process
US7208379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Oct 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.