Integrated circuit metal silicide method
US7208409B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Jun 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.