Non-volatile semiconductor memory device allowing shrinking of memory cell
US7208751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2003 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Mar 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.