Split gate flash memory
US7208796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.