Semiconductor component assemblies having interconnects
US7208839B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric material disposed on a surface thereof, surrounding but not covering interconnect elements, such as bond pads, on that surface. A second semiconductor component substrate, such as a carrier substrate with interconnect elements such as terminal pads, is adhered to the first semiconductor component substrate, forming a semiconductor package assembly having interconnect voids between the corresponding interconnect elements. A flowable conductive material is then injected into each interconnect void using an injection needle that passes through one of the substrates into the interconnect void, forming a conductive interconnect between the bond pads and terminal pads of the substrates. In another embodiment, a conductive material is preplaced into the interconnect voids and ultrasonically heated to a flowable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.