Routing design to minimize electromigration damage to solder bumps
US7208843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | May 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.