On die termination circuit
US7208973B2 · kind B2 · utility
7Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Feb 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an on die termination circuit. The on die termination circuit used in a DDR2 employs transmission gates as pull-up and pull-down switches, equalizes pull-up and pull-down resistance values by changing connection relations between switches and resistors, and maintains a constant voltage of an input pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.