Synchronous clock generator including duty cycle correction
US7208989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | May 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.