Memory structure for providing decreased leakage and bipolar current sensitivity
US7209394B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Nov 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit. In one embodiment, the memory circuit includes a first one-hot multiplexer having a first plurality of local bitlines and a second one-hot multiplexer having a second plurality of local bitlines. Each of the first and second pluralities of local bitlines includes is coupled to a memory cell, and includes a passgate arranged on its respective local bitline to allow access to the cell. The first one-hot multiplexer and the second one-hot multiplexer are coupled together such that the highest order local bitline (i.e. corresponding the highest order bit in the group) is coupled to the lowest order bitline of the second one-hot multiplexer, and vice-versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.