Scalable bus structure
US7209998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Mar 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.