Maintaining processor execution during frequency transitioning
US7210054B2 · kind B2 · utility
12Cited by
25References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2002 |
| Grant date | Apr 24, 2007 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.