Semiconductor device with shallow trench isolation and its manufacture method
US7211480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Jul 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.