Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage
US7211844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Apr 25, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/724
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.