Three-dimensional multichip stack electronic package structure
US7211886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2006 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | May 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.