Method and system for a two stage pipelined instruction decode and alignment using previous instruction length
US7213129B1 · kind B1 · utility
6Cited by
16References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.