Using thread urgency in determining switch events in a temporal multithreaded processor unit
US7213134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit of the invention has multiple instruction pipelines for processing multi-threaded instructions. Each thread may have an urgency associated with its program instructions. The processing unit has a thread switch controller to monitor processing of instructions through the various pipelines. The thread controller also controls switch events to move from one thread to another within the pipelines. The controller may modify the urgency of any thread such as by issuing an additional instruction. The thread controller preferably utilizes certain heuristics in making switch event decisions. A time slice expiration unit may also monitor expiration of threads for a given time slice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.