Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and software product for executing the correction method
US7213226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Aug 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.