High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system
US7213248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | May 1, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.