Manufacturing process and structure of power junction field effect transistor
US7214601B2 · kind B2 · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Aug 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.