Space-efficient package for laterally conducting device
US7215012B2 · kind B2 · utility
14Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2003 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Dec 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.