Triaxial through-chip connection
US7215032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing an inner and outer perimeter side wall of the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material so that the metal on the outer perimeter side wall and on the inner perimeter side wall are both electrically separated from each other and from the electrically conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.