Semiconductor memory device that requires refresh operations
US7215589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2006 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/783
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the relevant address within one refresh cycle in response to a fact that the ROM circuit detects the relevant address. The multiple refresh control circuit excludes a pattern having a risk that a power supply potential or a ground potential varies greatly such as a pattern that the multiple refresh occurs continuously. With this arrangement, a refresh defective cell can be saved while restricting the variation in the power supply potential or the ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.