Processor with software-controlled programmable service levels
US7215675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5675
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.