Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7216204B2 · kind B2 · utility
61Cited by
287References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2002 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Aug 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Stored units of information related to packet processing are associated with identifiers, each of which is maintained as an entry in a Content Addressable Memory (CAM). Each entry includes status information associated with the information unit with which the identifier is associated. The status information is used to determine validity of the information unit with which the status information is associated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.